In an integrated circuit chip, the various functions performed by the logic elements and other components on the chip are synchronized by a chip clock signal. The clock signal controls the rate of logic operations performed on the chip and is crucial to the overall operation of the chip.
In prior art implementations, an external clock is supplied to the chip and the logic functions are expected to work correctly at the rate of the supplied clock. However, the individual logic elements located on the chip are dependent on chip temperature, chip operating voltage and process variables such as channel conductance and threshold voltage. Therefore, if the clock rate does not compensate for the variations in chip operating conditions, the chip may not be able to perform properly at the chip clock rate.
For example, assume a microprocessor chip is designed to function at 100 MHz at optimum operating conditions. If the chip is subjected to increased temperature conditions, the rate at which the individual logic elements on the chip perform can be expected to slow down. If the clock remains at 100 MHz, the logic functions will not be able to perform at this clock rate and the chip may output erroneous results or fail to perform.
Therefore, in prior art implementations, the chip logic functions must be designed for the worst case conditions of environmental variables (temperature, voltages, etc.). However, in practice, the variables are rarely all at the worst case conditions at the same time. Therefore, the chip logic is often operating at a clock rate below its optimum.
In other prior art implementations using conventional phase locked loop (PLL) or other mixed analog-digital approaches, the analog nature of the clock control signal makes the operation very sensitive to noise. Performance optimization becomes difficult especially when integration with very large scale high speed digital functions is necessary, since digital switching operations tend to induce a large amount of switching noise.
In view of the above, a need exists for providing a chip clock that supplies an accurate clocking signal to the chip logic functions, but also compensates for variations in the operating conditions on the chip itself. It additionally is desirable to provide a clock signal using a digital design which can be continuously updated based on the current chip conditions to enable the chip to operate at maximum efficiency.